`timescale 1ns/1ns // ????????1ns????????1ns

module hello_tb;
	reg clk;
	reg reset;
	wire [1:0] q;

	hello uut (.clk(clk), .reset(reset), .q(q));

	initial begin
		clk = 1'b0;
		reset = 1'b0;

		#2 reset = 1'b1;
		#2 reset = 1'b0;
	end

	always #1 clk = ~clk;

endmodule
